1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to transistor architectures that enable an extended functionality of transistor devices, thereby providing the potential for simplifying the configuration of circuit elements, such as registers, static RAM cells and the like.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a great number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Although immense progress has been made over the recent decades with respect to increased performance and reduced feature sizes of the circuit elements, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed thereof. However, the continuing scaling of feature sizes involves great efforts in re-designing process techniques and developing new process strategies and tools to comply with new design rules. Generally, in complex circuitry including complex logic portions, MOS technology is presently a preferred manufacturing technique, in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits including logic portions fabricated by MOS technology, a large number of field effect transistors (FETs) are provided that are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which may influence, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain terminal and a source terminal.
On the basis of field effect transistors, more complex circuit components may be created. For instance, storage elements in the form of registers, static RAM (random access memory) and dynamic RAM represent an important component of complex logic circuitries. For example, during the operation of complex CPU cores, a large amount of data has to be temporarily stored and retrieved, wherein the operating speed and the capacity of the storage elements significantly influence the overall performance of the CPU. Depending on the memory hierarchy used in a complex integrated circuit, different types of memory elements are used. For instance, registers and static RAM cells are typically used in the CPU core due to their superior access time, while dynamic RAM elements are preferably used as working memory due to the increased bit density compared to registers or static RAM cells. Typically, a dynamic RAM cell comprises a storage capacitor and a single transistor, wherein, however, a complex memory management system is required to periodically refresh the charge stored in the storage capacitors, which may otherwise be lost due to unavoidable leakage currents. Although the bit density of DRAM devices may be very high, a charge has to be transferred from and to storage capacitors in combination with periodic refresh pulses, thereby rendering these devices less efficient in terms of speed and power consumption when compared to static RAM cells. On the other hand, static RAM cells require a plurality of transistor elements to allow the storage of an information bit.
In order to reduce the number of transistor elements in static RAM cells, it has, therefore, been proposed to use planar field effect transistors with increased functionality compared to conventional field effect transistors by providing a modified body region of the field effect transistors on the basis of an additional doped region to provide a “second” channel region, which may impart a different transistor characteristic to these so-called double channel planar field effect transistors. That is, by providing an additional second channel region in the body of the planar field effect transistor, the trans-conductance of the transistor may be modified to generate a local maximum of the drain source current, thereby obtaining a three-state transfer slope, which may be used for providing basic transistor circuits with increased functionality. For instance, in conventional planar transistor architectures, a RAM cell with a reduced number of transistors may be provided.
FIG. 1a schematically illustrates a cross-sectional view of a conventional planar transistor element 100 that may be used in forming an electronic circuit, such as a RAM cell, with enhanced functionality or with a reduced number of circuit elements compared to conventional strategies by taking advantage of the three-state transistor transfer slope. The transistor element 100 comprises a substrate 101, which may be any appropriate substrate, such as a bulk semiconductor substrate, an insulating substrate having formed thereon a crystalline semiconductor layer and the like. For example, the substrate 101 may represent a bulk silicon substrate or a silicon-on-insulator (SOI) substrate, since presently, and in the near future, the majority of complex and integrated circuits are and will be fabricated on the basis of silicon. A substantially crystalline semiconductor region 102 is formed on the substrate 101 and comprises a specified dopant material to provide a desired conductivity type of the region 101. In the example shown in FIG. 1a, the semiconductor region 102 is doped to provide a P-type conductivity. Furthermore, drain and source regions 104 are formed adjacent to the region 102 and include a dopant material that imparts a conductivity type to the drain and source regions 104 that is opposite to the conductivity type of the semiconductor region 102. In the example shown, the drain and source regions 104 are heavily doped so that corresponding PN junctions are formed along interfaces between the drain and source regions 104 and the semiconductor region 102. Moreover, a channel region 103 is located between the drain and source regions 104 according to typical planar transistor configurations and comprises a first channel sub-region 103A that is oppositely doped with respect to the drain and source regions 104. For example, the first channel sub-region 103A may be considered a “conventional” channel region of a conventional enhancement transistor. Furthermore, the channel region 103 comprises a second channel sub-region 103B that is oppositely doped with respect to the first channel sub-region 103A and may therefore be considered a “depletion” channel. In the example shown, the planar field effect transistor 100 of FIG. 1a represents an N-type transistor and therefore the first channel sub-region 103A is P-doped and the second channel sub-region 103B is N-doped. The transistor element 100 further comprises a gate electrode 105 that is located above the channel region 103, i.e., above the first and second channel sub-regions 103A, 103B, thereby enabling a capacitive coupling of the gate electrode 105 to the channel region 103. Furthermore, in the example shown, the gate electrode 105 is separated from the channel region 103 by a gate insulation layer 106 formed on the top surface of the basic semiconductor layer, in which the drain and source regions 104 and the channel region 103 are provided. The gate insulation layer 106 may be comprised of silicon dioxide and/or silicon nitride and/or silicon oxynitride and/or high-k dielectric materials and the like, according to well-established planar transistor architectures. The transistor element 100, which may also be referred to as a double channel transistor due to the configuration of the channel region 103, further comprises sidewall spacers 107 formed on sidewalls of the gate electrode 105 in accordance with well-established planar transistor configurations. Furthermore, other components, such as metal silicide regions in the drain and source regions 104 and the gate electrode 105 may be provided to enhance overall conductivity and thus transistor performance. For convenience, any such performance enhancing components are not illustrated. In some conventional approaches for forming a planar double channel transistor, a contact area 108 is provided that connects to a portion of the semiconductor region 102, which in combination with the channel region 103 may also be referred to as the body region of the transistor 100. The contact area 108 is thus electrically connected to the body region while at the same time being electrically isolated from the drain and source regions 104 by the corresponding PN junctions. By means of the contact area 108, the body region of the transistor 100 may be connected to an appropriate reference voltage, which may enhance the controllability of the transistor 100.
The transistor 100 may be formed on the basis of well-established conventional transistor manufacturing process flows including the fabrication of appropriate isolation structures (not shown) in order to define respective active areas for a plurality of transistors, such as the transistor 100. Next, the basic doping of the body region of the transistor may be established by well-established implantation techniques, followed by the incorporation of an opposite dopant species in order to define the second channel sub-region 103B within the body region. Next, the gate electrode 105 in combination with the gate insulation layer 106 may be formed, for instance by forming the gate dielectric material by oxidation and/or deposition followed by the deposition of an appropriate gate electrode material, such as polysilicon and the like, which may subsequently be patterned on the basis of sophisticated lithography techniques. Thereafter, an offset spacer (not shown) may be formed, if required, and an implantation sequence may be performed to define a first portion of the drain and source regions 104, which may also include a corresponding halo implantation process. That is, during the halo implantation, a conductivity type may be induced, for instance on the basis of a tilted implantation process, which is of opposite conductivity type compared to that obtained by the dopant species for the drain and source regions. Consequently, in addition to adjusting the dopant gradient at the PN junctions, the second channel sub-region 103B may also be “isolated” from the drain and source regions due to the counter doping obtained by the halo implantation, which may result in a higher dopant concentration at the areas between the second channel sub-region 103B and the drain and source regions so as to impart an overall conductivity to these areas that correspond to the conductivity type of the remaining body region. Thereafter, the spacer structure 107 may be formed in accordance with well-established spacer techniques. The drain and source regions 104 may be completed by respective ion implantation processes, followed by appropriately designed anneal cycles in order to activate the dopant species and re-crystallize implantation-induced damage, thereby also adjusting the final dopant profile.
FIG. 1b schematically illustrates the functional behavior of the double channel transistor 100. In FIG. 1b, the conductivity of the transistor 100, i.e., the conductivity of the channel region 103, is plotted along the vertical axis in arbitrary units, and the control voltage VG supplied to the gate electrode 105 is shown on the horizontal axis. The double channel transistor 100 exhibits a significantly modified trans-conductance compared to conventional single channel planar field effect transistors due to the presence of the second channel region in that the conductivity of the transistor 100 has a more or less pronounced local maximum. As illustrated, when the control voltage VG exceeds a first threshold voltage VT1, a typical increase of the conductivity may be obtained, as is the case for conventional planar enhancement transistors. At a second threshold voltage VT2, however, a significant drop of the conductivity with increasing control voltage VG may be observed, resulting in a local minimum at a third threshold voltage VT3 at which a further increase in conductivity with an increasing control voltage VG may be observed. Consequently, the local maximum or minimum at voltages VT2 and VT3, respectively, may provide an intermediate stable state in the transfer slope of the transistor 100, which may be advantageously used in order to build basic electronic circuits of increased functionality for the same number of circuit elements as in conventional designs, while in other cases a desired functionality may be accomplished on the basis of a reduced number of circuit elements by replacing one or more of the conventional planar field effect transistors by a planar double channel transistor, such as the transistor 100.
Although significant advantages may be gained with respect to increased functionality and/or reduced area consumption of basis electronic circuits, such as RAM cells, which may be provided on the basis of less than 6 planar double channel transistors, a further advance with respect to increased information density per chip unit area may be difficult to be achieved due to the limitations of appropriate control of current flow between the source and drain regions in planar transistor configurations. In particular, for device generations with highly scaled transistor elements including gate electrode structures having a length of 30 nm and less, extremely complex manufacturing techniques may have to be applied to account for the reduced controllability of the transistor behavior. In the corresponding transistor elements, extremely complex dopant profiles, in combination with sophisticated gate electrode structures, may have to be used, possibly in combination with a plurality of additional mechanisms, such as strain-inducing mechanisms and the like, in order to obtain the required performance with respect to drive current and controllability. Consequently, the provision of a second channel region may contribute to a corresponding high degree of complexity of establishing an appropriate dopant profile in planar field effect transistors having a second channel region. Thus, in view of a further scalability of the overall device dimensions, drive current capability and/or channel controllability may be difficult to be realized according to conventional techniques, as described above.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.